Semiconductor-on-insulator (SOI) technology, which represents an advance over traditional bulk silicon processes, was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from the bulk substrate by an electrically insulating layer. One advantage of isolating circuitry from the bulk substrate is a dramatic decrease in parasitic capacitance which allows access to a more desirable power-speed performance horizon. Therefore, SOI structures are particularly appealing for high frequency applications such as radio frequency (RF) communication circuits. As consumer demand continues to tighten the power constraints faced by RF communication circuits, SOI technology continues to grow in importance.
A typical SOI structure 100 is shown in FIG. 1. The SOI structure 100 includes a substrate layer 101, an insulator layer 102, and an active layer 103. The substrate layer 101 is typically a semiconductor material such as silicon. The insulator layer 102 is a dielectric which is often silicon dioxide formed through the oxidation of the substrate layer 101 in situations where the substrate layer 101 is silicon. The active layer 103 includes an active device layer 104 and a metallization or metal interconnect layer 105, which further include a combination of dopants, dielectrics, polysilicon, metal wiring, passivation, and other layers, materials or components that are present after circuitry has been formed therein. The circuitry may include metal wiring 106 (e.g. in the metal interconnect layer 105); passive devices such as resistors, capacitors, and inductors; and active devices such as a transistor 107 (e.g. in the active device layer 104).
As used herein and in the appended claims, the region in which signal processing circuitry is formed on an SOI structure is referred to as the “active layer” of the SOI structure. For example, in FIG. 1 the active layer is the active layer 103 which includes devices or components such as the transistor 107 and the metal wiring 106. When reference is made particularly to the layer of active semiconductor material that forms the active devices themselves the term “active device layer” (e.g. 104) is used instead. For example, in FIG. 1 the active device layer 104 is the portion of the active layer 103 that contains the transistor 107 and does not include the metal wiring 106 of the metal interconnect layer 105.
Also as used herein and in the appended claims, the “top” of the SOI structure 100 references a top surface 108 while the “bottom” of the SOI structure 100 references a bottom surface 109. This orientation scheme persists regardless of the relative orientation of the SOI structure 100 to other frames of reference, and the removal of layers from, or the addition of layers to the SOI structure 100. Therefore, the active layer 103 is always “above” the insulator layer 102. In addition, a vector originating in the center of the active layer 103 and extending towards the bottom surface 109 will always point in the direction of the “back side” of the SOI structure 100 regardless of the relative orientation of the SOI structure 100 to other frames of references, and the removal of layers from, or the addition of layers to the SOI structure 100.
Consumer demand continues to tighten the constraints on the quality and performance of RF devices. These constraints directly affect the required linearity and precision of the signals that are produced and decoded by RF circuits. Among other requirements, signals in one portion of a circuit must be kept from affecting and degrading signals in another portion of the circuit. This effect is called cross talk. The mitigation of cross talk is of critical importance for RF communication circuits because the impedance of certain parasitic pathways within a circuit tends to reach a minimum at frequencies that are used to carry signals in RF circuits. Since these same parasitic pathways connect nodes within a circuit that carry differing signals, the problem of cross talk is especially problematic for RF applications. In addition, it is critically important for the parasitic capacitances to which the signals within a circuit may be exposed not to be signal dependent. This requirement is critical because it is difficult to calibrate out an error that is signal dependent, and such errors are inherently nonlinear.
One solution to the problem of cross talk in electronic circuits is the use of a high resistivity substrate. With reference to FIG. 1, increasing the resistance of the substrate layer 101 reduces cross talk by maintaining the impedance of the parasitic paths through the substrate higher than the impedance would be without an increased substrate resistance. Materials used for the substrate layer 101 typically include very lightly doped silicon such that the substrate layer 101 takes on some of the characteristics of an insulator. The use of high resistivity substrates has proven capable of extending the benefit of SOI structures for RF communication circuits by roughly two orders of frequency magnitude.
Although high resistivity substrates are capable of reducing substrate loss when they are used in SOI processes, they are highly susceptible to another phenomenon called parasitic surface conduction. The problem of parasitic surface conduction and a potential solution can be explained with reference again to FIG. 1. As mentioned previously, the typical high resistivity substrate device insulator layer 102 is silicon dioxide, and the substrate layer 101 is high resistivity silicon. The problem of parasitic surface conduction comes from the fact that the lightly doped silicon that forms the substrate layer 101 is capable of terminating field lines, but a thin surface region 110 of the substrate layer 101 can be formed into an inversion or accumulation region as charge carriers are affected by signal voltages in the active layer 103. The degree to which charge carriers in the region 110 are displaced is directly altered by the signals in the active layer 103. As a result, the capacitance of the junction between the substrate layer 101 and the active layer 103, as seen by the active layer, depends on the voltage applied. This capacitance results in nonlinearity and a concomitant loss of signal purity. In addition, an applied voltage can invert this interface on the side of the substrate layer 101 and create a channel-like layer within the region 110 where charge can move very easily in a lateral direction despite the fact that the substrate layer 101 is highly resistive. Therefore, this effect can also lead to signal-degrading cross talk in RF communication circuits.
A solution to the problem of the undesirable creation of the channel-like layer in region 110 has commonly been to form a trap rich layer along the top of the substrate layer 101 within the region 110. The presence of this trap rich layer effectively combats parasitic surface conduction because the trap rich layer significantly degrades the carrier lifetimes of the charge carriers in the region 110. Since the carriers cannot travel far, therefore, the effective resistance of the substrate layer 101 is preserved and the capacitance as seen by the active layer 103 is not as dependent upon the signals in the active layer 103.
A problem with the trap rich layer in region 110, however, is that when the trap rich layer is formed prior to the subsequent processing for the formation of the structures in the active layer 103, those later processing steps can degrade the trap rich layer. Processing of semiconductor devices and in particular the production of active devices in the active layer 103 generally involves high temperature processes conducted at temperatures from 1000° C. to 1100° C. High temperature processing of semiconductor structures acts to anneal defects in a semiconductor crystal lattice. This effect is commonly utilized to enhance the electrical properties of electrical circuits. However, contrary to usual applications, the performance of trap rich layers formed from amorphous or polycrystalline silicon crystal patterns is actually decreased when imperfections are annealed out since the number of traps is decreased.